1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, particularly, to a semiconductor device and a manufacturing method thereof which can prevent characteristic deterioration due to metallic contamination which occurs in a backside grinding process and a package assembly process performed after formation of desired devices, wiring, and insulating film on a main surface of a semiconductor substrate.
2. Description of the Related Art
A conventional semiconductor device, shown in FIG. 2, is fabricated as follows. In accordance with a process flowchart shown in FIG. 1, electronic devices 3, wiring 4, an interlayer insulating film 5, and the like, are formed on a surface of a silicon substrate 1. Thereafter a substrate's backside 6 is ground so that the substrate can have a desired thickness. Subsequently, the substrate is diced into chips and, in a TSOP assembly process, a lead frame with LOC tape and a chip are bonded through the LOC tape. Then, after wire bonding, resin sealing is carried out.
As described in Japanese Patent Application Publication (JP-A) No. H1-67922, in a conventional semiconductor device, desired electronic devices, wiring, an insulating film and the like are formed after a gettering layer for counteracting metallic contamination, which is introduced in formation processes, is formed on a substrate's backside.
A conventional semiconductor device has the following drawbacks. When a backside is ground as shown in FIG. 2, the ground surface receives grinding damages such as dislocations 7 and cracks 8, as shown in FIG. 3, and metallic contamination is also introduced into the areas of grinding damages. Moreover, in the subsequent dicing process, dicing damages, which are similar to grinding damages, are introduced into the side surfaces of chips and metallic contamination is also introduced into the side surfaces of the chips.
In addition, after bonding of a lead frame and chips through the LOC tape, the chips in the above-mentioned state are then exposed to thermal process through baking (30 minutes at 150 degrees centigrade, and 90 minutes at 230 degrees centigrade) as well as resin sealing (several tens of minutes at 180 degrees centigrade). Therefore, the metal introduced during the grinding or dicing process is affected by the thermal process in the assembly processes and the metal attached to the ground surface reaches an electronic device formed on the main surface of the substrate. For example, in the foregoing TSOP assembly process, in the case of resin sealing, thermal process of several ten minutes at 180 degrees centigrade is applied to the chips. Therefore, where metal such as copper or the like is attached to a ground surface, a diffusion length thereof within the substrate (silicon) becomes several 100 μm. In addition, since the thickness of the chip after the backside grinding is also several 100 μm, the metal can easily reach an electronic device formed on the substrate's main surface.
As described above, once a contaminating metal reaches an electronic device on a main surface of a substrate, various problems become apparent. For example, when a contaminating metal reaches the depletion layer of a source/drain junction, it leads to the formation of surface state and thus causes the generation of junction leakage current. Furthermore, if a contaminating metal reaches a gate insulating film, insulating film leakage current increases. Because of such increases in the leakage current, characteristics of an electronic device are deteriorated. The above-mentioned problem has been increasingly serious particularly in recent years as a multi-chip package, wherein chips with a reduced thickness of about 100 μm are stacked, has been commercialized.
A backside gettering layer formed in a conventional semiconductor device described in Japanese Patent Application Publication No. H1-67922 has a gettering effect against metallic contamination introduced in formation processes of electronic devices and the like. However, since a backside of a substrate in a wafer state is ground to have a desired thickness before being assembled onto a package assembly, the gettering layer is removed by the grinding. Hence, the gettering layer loses its gettering capability against metallic contamination introduced in the backside grinding and package assembly. Because the backside gettering layer is removed by backside grinding, it is not feasible to prevent characteristic deterioration caused by metallic contamination introduced after the backside grinding.
Nevertheless, since the backside receives grinding damages caused by the backside grinding, which produces gettering capability remains, albeit only slightly. Yet, the gettering capability produced by a grinding damage layer is not sufficient and is not able to suppress the above-described characteristic deterioration. Particularly, in recent years, adverse effects of metal contamination from a backside towards a main surface have been significant more than ever since a chip thickness in a multi chip package and the like after backside grinding has been reduced to around 100 μm.